Un-do extraneous changes before merging back into source branch

This commit is contained in:
akuker
2020-07-19 14:59:40 -05:00
parent 7b10c2299f
commit a033451863
5 changed files with 36 additions and 125 deletions

View File

@@ -1,65 +0,0 @@
#!/usr/bin/python
import sys
outfile = open('data.json', 'w')
infile = open('timing_drawer.txt','r')
print("{signal: [", file=outfile)
firstline = infile.readline()
num_columns = len(firstline.split(";"))
# Skip the time field
field_num = 1
while (field_num < num_columns):
var = firstline.split(";")
var2 = var[field_num].split("=")
field_name = var2[0]
infile.seek(0)
print(" {name: '" + field_name + "', wave: '", file=outfile, end='')
prev_val = ''
if (field_name == "DATA"):
for line in infile:
value_pair = line.split(";")[field_num]
z = value_pair.split("=")[1].strip().replace(".","")
if(z == prev_val):
out = '.'
prev_val = z
elif (z == '00'):
out = '0'
else:
out = '2'
print(out, file=outfile, end='')
prev_val = z
print("', data: [", file=outfile, end='')
infile.seek(0)
for line in infile:
value_pair = line.split(";")[field_num]
z = value_pair.split("=")[1].strip().replace(".","")
if(z == prev_val):
continue
print("'" + z + "', ", file=outfile, end='')
prev_val = z
print("]},", file=outfile)
else:
for line in infile:
value_pair = line.split(";")[field_num]
z = value_pair.split("=")[1]
if(z == prev_val):
z = '.'
else:
prev_val = z
print(z, file=outfile, end='')
print("'},", file=outfile)
field_num = field_num + 1
print("]}", file=outfile)
outfile.close()

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@@ -43,14 +43,6 @@
// Disk // Disk
// //
//=========================================================================== //===========================================================================
#ifndef DISK_LOG
#define DISK_LOG
#endif // DISK_LOG
#ifndef RASCSI
#define RASCSI
#endif // RASCSI
#ifdef RASCSI #ifdef RASCSI
#define BENDER_SIGNATURE "RaSCSI" #define BENDER_SIGNATURE "RaSCSI"
@@ -6447,16 +6439,14 @@ void FASTCALL SASIDEV::Selection()
return; return;
} }
// Wait for this monitor target to assert the selection spdlog::trace(
// before moving on to the selection phase. "Selection Phase ID=%d (with device)", ctrl.id);
if(ctrl.bus->GetBSY())
{
// Phase change // Phase change
ctrl.phase = BUS::selection; ctrl.phase = BUS::selection;
spdlog::trace(
"[ID %d] Selection Phase (with device)", ctrl.id);
}
// Raise BSY and respond
ctrl.bus->SetBSY(TRUE);
return; return;
} }
@@ -6495,14 +6485,6 @@ void FASTCALL SASIDEV::Command()
ctrl.bus->SetCD(TRUE); ctrl.bus->SetCD(TRUE);
ctrl.bus->SetIO(FALSE); ctrl.bus->SetIO(FALSE);
// Wait until target sets the following condition:
// MSG = FALSE
// CD = TRUE
// IO = FALSE
if (ctrl.bus->GetMSG() || !ctrl.bus->GetCD() || ctrl.bus->GetIO()) {
return;
}
// Data transfer is 6 bytes x 1 block // Data transfer is 6 bytes x 1 block
ctrl.offset = 0; ctrl.offset = 0;
ctrl.length = 6; ctrl.length = 6;
@@ -8037,7 +8019,6 @@ BUS::phase_t FASTCALL SCSIDEV::Process()
return ctrl.phase; return ctrl.phase;
} }
// spdlog::trace("ID {} in phase {}",ctrl.id,ctrl.phase);
// Phase processing // Phase processing
switch (ctrl.phase) { switch (ctrl.phase) {
// Bus free phase // Bus free phase
@@ -8162,20 +8143,14 @@ void FASTCALL SCSIDEV::Selection()
return; return;
} }
spdlog::trace(
"Selection Phase ID={} (with device)", ctrl.id);
// Phase setting
ctrl.phase = BUS::selection; ctrl.phase = BUS::selection;
// Wait for this monitor target to assert the selection // Raise BSY and respond
// before moving on to the selection phase. ctrl.bus->SetBSY(TRUE);
if(ctrl.bus->GetBSY())
{
// Phase change
spdlog::trace(
"[ID {} Selection Phase (with device)", ctrl.id);
}
else{
spdlog::trace("[ID {}] Selection phase", ctrl.id);
}
return; return;
} }

View File

@@ -141,25 +141,6 @@
#define PIN_BSY 26 // BSY #define PIN_BSY 26 // BSY
#define PIN_SEL 27 // SEL #define PIN_SEL 27 // SEL
#define ALL_SCSI_PINS \
((1<<PIN_DT0)|\
(1<<PIN_DT1)|\
(1<<PIN_DT2)|\
(1<<PIN_DT3)|\
(1<<PIN_DT4)|\
(1<<PIN_DT5)|\
(1<<PIN_DT6)|\
(1<<PIN_DT7)|\
(1<<PIN_DP)|\
(1<<PIN_ATN)|\
(1<<PIN_RST)|\
(1<<PIN_ACK)|\
(1<<PIN_REQ)|\
(1<<PIN_MSG)|\
(1<<PIN_CD)|\
(1<<PIN_IO)|\
(1<<PIN_BSY)|\
(1<<PIN_SEL))
#endif #endif
#ifdef CONNECT_TYPE_FULLSPEC #ifdef CONNECT_TYPE_FULLSPEC
@@ -296,6 +277,26 @@
#define PIN_SEL 23 // SEL #define PIN_SEL 23 // SEL
#endif #endif
#define ALL_SCSI_PINS \
((1<<PIN_DT0)|\
(1<<PIN_DT1)|\
(1<<PIN_DT2)|\
(1<<PIN_DT3)|\
(1<<PIN_DT4)|\
(1<<PIN_DT5)|\
(1<<PIN_DT6)|\
(1<<PIN_DT7)|\
(1<<PIN_DP)|\
(1<<PIN_ATN)|\
(1<<PIN_RST)|\
(1<<PIN_ACK)|\
(1<<PIN_REQ)|\
(1<<PIN_MSG)|\
(1<<PIN_CD)|\
(1<<PIN_IO)|\
(1<<PIN_BSY)|\
(1<<PIN_SEL))
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
// //
// Constant declarations(GPIO) // Constant declarations(GPIO)
@@ -505,8 +506,6 @@ public:
void FASTCALL SetIO(BOOL ast); void FASTCALL SetIO(BOOL ast);
// Set IO signal // Set IO signal
void FASTCALL SetAct(BOOL ast) { PinSetSignal(PIN_ACT, ast);}
BOOL FASTCALL GetREQ(); BOOL FASTCALL GetREQ();
// Get REQ signal // Get REQ signal
void FASTCALL SetREQ(BOOL ast); void FASTCALL SetREQ(BOOL ast);

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@@ -15,6 +15,9 @@
#define LOGINFO(...) \ #define LOGINFO(...) \
do{char buf[256]; snprintf(buf, 256,__VA_ARGS__); spdlog::info(buf);}while(0) do{char buf[256]; snprintf(buf, 256,__VA_ARGS__); spdlog::info(buf);}while(0)
#define LOGTRACE(...) \
do{char buf[256]; snprintf(buf, 256,__VA_ARGS__); spdlog::trace(buf);}while(0)
//=========================================================================== //===========================================================================
// //

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@@ -1147,4 +1147,3 @@ init_exit:
return ret; return ret;
#endif // BAREMETAL #endif // BAREMETAL
} }